Timing diagram of 8085, opcode fetch cycle, memory read & write cycle, I/O Read and write cycle.

                Timing Diagram of 8085

Timing diagram:-  it is a graphical representation. it represents the execution time taken by each instruction in a graphical format. the execution time is represented in T-states.

Instruction Cycle:- the time required to execute an instruction.

Machine Cycle:- the time required to access the memory or I/O  devices.

T-states:-  

• the machine cycle and instruction cycle takes multiple clock periods.
• A portion of an operation carried out in one system clock periods is called as T-STATES.

          

       NOTE: Time period, T= 1/f ; where f = internal clock frequency.

                       

TIMING DIAGRAMS:-

• The 8085 microprocessor has 7 basic machine cycle. they are-

1. Op-code Fetch cycle (4T or 6T)
2. Memory read cycle (3T)
3. Memory write cycle (3T)
4. I/O read cycle (3T)
5. I/O write cycle (3T)
6. interrupt Acknowledge cycle (6T or 12T)
7. Bus idle cycle 

   

1. OPCODE FETCH CYCLE(4T or 6T ).

• The Opcode fetch cycle, fetches the instructions from memory and delivers it to the instruction register of the microprocessor.
• Opcode fetch machine cycle consists of 4 T-states.

 T1 STATE:

During the T1 state, the contents of the program counter are placed on the 16 bit address bus. the higher order 8 bits are transferred to the the address bus (A8-A15) and lower order 8 bits are transferred to multiplexed A/D (AD0-AD7) bus. 

 

ALE ( Address latch enable): signal goes high. As soon as ALE goes high, the memory latches the AD0-AD7 bus. At the middle of the T state the ALE goes low..

T2 States: During the beginning of this state, the RD’ signal goes low to enable memory. It is during this state, the selected memory location is placed on D0-D7 of the Address/Data multiplexed bus.

T3 States: In the previous state the Opcode is placed in D0-D7 of the A/D bus. In this state of the cycle, the Opcode of the A/D bus is transferred to the instruction register of the microprocessor. Now the RD’ goes high after this action and thus disables the

memory from A/D bus.

T4 States: In this state the Opcode which was fetched from the memory is decoded.

2. MEMORY READ CYCLE (3T):

• These machine cycles have 3 T-states.

T1 STATE:

• The higher order address bus (A8-A15) and lower order address and data multiplexed (AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) so that complete 16-bit address are available.

• The mp identifies the memory read machine cycle from the status signals IO/M’=0, S1=1, S0=0. This condition indicates the memory read cycle.

T2 STATE:

• Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. RD’ goes LOW.

 T3 STATE:

• The data which was loaded on the previous state is transferred to the microprocessor. In the middle of the T3 state RD’ goes high and disables the memory read operation. The data which was obtained from the memory is then decoded.

 3. MEMORY WRITE CYCLE:

• These machine cycles have 3 T-states.

T1 STATE: 

• The higher order address bus (A8-A15) and lower order address and data multiplexed (AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) so that complete 16-bit address are available.

• The mp identifies the memory read machine cycle from the status signals IO/M’=0, S1=0, S0=1. This condition indicates the memory read cycle.

T2 STATE:

• Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. WR’ goes LOW.

T3 SATATE:

• In the middle of the T3 state WR’ goes high and disables the memory write operation. The data which was obtained from the memory is then decoded.

4. I/O READ CYCLE (3T):

5. I/O WRITE CYCLE:

                STA INSTRUCTION

                                        

                                        E.g = STA 526A H

                                    

It require 4 m/c cycles & 13 T states.

1.opcode fetch(4T)

2.memory read(3T)

3.memory read(3T)

4.Memory write(3T)